1. Field of the Invention
The present invention relates to an overlapping trench gate semiconductor device and its manufacturing method, and more particularly to an overlapping trench gate semiconductor device having a lower parasitic capacitance between a gate electrode and a drain electrode and its manufacturing method.
2. Description of the Prior Art
A trench gate semiconductor device is primarily used in power management such as switching power supplies, power control ICs of computer systems or peripherals, power supplies of backlight, motor controllers, etc.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a cross-sectional view of a prior art trench gate semiconductor device. As illustrated in FIG. 1, the prior art trench gate semiconductor device 10 includes an N type substrate 12, an N type epitaxial layer 14, a plurality of trenches 16, a gate insulation layer 18, a plurality of gate electrodes 20, and a source metal layer 22. The N type epitaxial layer 14 is disposed on the N type substrate 12 and each of the trenches 16 is disposed on the N type epitaxial layer 14. The gate insulation layer 18 is disposed on surfaces of the trenches 16, and each of the gate electrodes 20 fill each of the trenches 16. Also, the gate insulation layer 18 electrically insulates the gate electrodes 20 from the source metal layer 22. A plurality of P type doped base regions 24 are formed on the N type epitaxial layer 14 and an N type doped source region 26 is formed on each P type doped base region 24. Furthermore, a P type heavily doped region 28 is disposed in each P type doped base region 24. Each P type heavily doped region 28 is electrically connected to the source metal layer 22 through a contact plug 30. Moreover, a drain metal layer 32 of the prior art trench gate semiconductor device 10 is disposed on a bottom surface of the N type substrate 12.
Although the trench gate semiconductor device can provide a rapid switching rate of a power source, a spike effect would occur during the switching of the power source. In order to avoid the spike effect, a ratio (Ciss/Crss) between an input capacitance (Ciss) and a reverse transfer capacitance (Crss) is often increased to reduce the spike effect during the switching.
The prior art trench gate semiconductor device raises the Ciss/Crss ratio by forming a shielding electrode structure under the gate electrode structure, thereby reducing the parasitic capacitance (also known as the Crss) between the gate electrode and the drain electrode through the shielding electrode structure. Also, a typical Ciss is composed of the parasitic capacitance between the gate electrode and the source electrode and the parasitic capacitance between the gate electrode and the drain electrode; therefore, without changing the parasitic capacitance between the gate electrode and the source electrode, lowering the parasitic capacitance between the gate electrode and the drain electrode of the device could increase the Ciss/Crss ratio, which reduces the spike effect.
Since the shielding electrode structure is located under the gate electrode structure and both the shielding electrode structure and the gate electrode structure are in a same trench, forming the shielding electrode structure and the gate electrode structure requires numerous steps of deposition processes and etching processes which is not only time consuming, but also increases costs in processes. Therefore, methods of raising the Ciss/Crss ratio and reducing any additional manufacturing cost have become objectives in the industry.